Performance Improvement in Conventional 4-bit Static CMOS Carry Look-Ahead Adder by Modifying Carry-Generate and Propagate Terms

Conventional static CMOS design employing pull-up and pull-down network for implementing logic functions has been one of the most reliable and widely used design techniques over the years. However, high input impedance and transistor count remains a major problem which result in high silicon area, high power consumption and increased delay. This research focus on reducing power, delay and transistor count in Conventional Static CMOS based 4-bit Carry Look Ahead adder. The conventional static CMOS XOR and gates are replaced by Gate Diffusion Input technique and Pass Transistor logic based XOR and AND gates in the input side to enhance performance parameters and to reduce transistor count. Two new modified CLA adder have been proposed and their performance parameters have been compared with conventional circuit using Cadence simulation tools. The proposed designs showed significant performance improvement while keeping the advantages of static CMOS Logic.