A hardware architecture for Multiscale Retinex with Chromacity Preservation on an FPGA

Image-processing algorithms based on Retinex theory aim to model human color perception to enhance images with low contrast or poor illumination. In particular, the Multiscale Retinex with Chromacity Preservation (MSRCP) algorithm improves on the original Retinex by processing the image at multiple scales and adding a color balance step in postprocessing. Despite their advantages, multiscale Retinex algorithms are computationally intensive, and real-time video processing is not generally possible with general-purpose processor architectures. In this paper, we present a special-purpose hardware accelerator for the MSRCP algorithm. The accelerator introduces tradeoffs to the original formulation of MSRCP by reducing the magnitude of the scales and using a cumulative histogram in the color-balance stage. Despite these modifications, we show that the accelerator produces images that are visually almost identical to a software implementation of the original MSRCP algorithm. We implement our design on a Xilinx XC7A200T-1SBG484C FPGA, which is capable of processing 1280×720-pixel video at up to 94 frames per second, a speedup of 123x compared to a desktop computer running a software version of the algorithm.