A Power-Efficient Clock Distribution Network with Novel Repeater

In this paper, a repeater is proposed, which is employed for achieving enhanced power efficiency in clock distribution network (CDN). The total power that is consumed by the clock distribution networks, which is operating at high frequency is an essential challenge in modern synchronous integrated circuits with billions of deeply-scaled transistors. The new repeater has 71%, 30% reduction the overall power consumption as compared to Conventional, Split IO repeater in H-Tree CDN respectively. The dynamic power consumption is reduced without increasing the static power consumption, CDN with Proposed repeater circuit is much more efficient in power and delay reduction, which is implemented in UMC 65nm CMOS technology.