A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS

The increasing complexity of Internet-of-Things (IoT) applications and near-sensor processing algorithms is pushing the computational power of low-power, battery-operated end-node systems. This trend also reveals growing demands for high-speed and energy-efficient inter-chip communications to manage the increasing amount of data coming from off-chip sensors and memories. While traditional microcontroller interfaces such as SPIs cannot cope with tight energy and large bandwidth requirements, low-voltage swing transceivers can tackle this challenge, thanks to their capability to achieve several Gbps of the communication speed at milliwatt power levels. However, recent research on high-speed serial links focused on high-performance systems, with a power consumption significantly larger than the one of low-power IoT end-nodes, or on stand-alone designs not integrated at a system level. This article presents a low-swing transceiver for the energy-efficient and low-power chip-to-chip communication fully integrated within an IoT end-node system-on-chip, fabricated in CMOS 65-nm technology. The transceiver can be easily controlled via a software interface; thus, we can consider realistic scenarios for the data communication, which cannot be assessed in stand-alone prototypes. Chip measurements show that the transceiver achieves $8.46\times $ higher energy efficiency at $15.9\times $ higher performance than a traditional microcontroller interface such as a single-SPI.

I. Introduction

Pushed by the increasing complexity of near-sensor data analytics algorithms, the computational performance required by Internet-of-Things (IoT) end-nodes has increased dramatically in the last few years. Nowadays, near-sensor applications, such as convolutional neural network (CNN)-based image analysis and bio-metric processing, have to efficiently operate on large volumes of sensor data captured by microcontrollers as well as application parameters such as weights of CNNs. To deal with this increasing complexity, state-of-the-art system-on-chips (SoCs) have already achieved performance in the order of several Giga Operation per Seconds (GOPS) within a power envelope in the order of a few mW, exploiting parallelism, Instruction Set Architecture (ISA) specialization, and domain-specific acceleration [1]–[3].