Area- and Power-Efficient Staircase Encoder Implementation for High-Throughput Fiber-Optical Communications

This brief presents a VLSI architecture of a high-throughput, low-latency, and power staircase forward error correction (FEC) encoder. The designed encoder achieves low latency and memory overhead by splitting the parity generation matrix and precomputing partial parity bits for the next staircase block while generating the current staircase block. The proposed encoder is designed with a multistage pipelined architecture that enables high efficiency in terms of throughput and area. Using 65-nm CMOS technology, the synthesized encoder achieves 432 Gb/s when operating at 909 MHz, with the power consumption of 323 mW.