Algorithm and Architecture Design of a Hardware-Efficient Frame Rate Upconversion Engine

Owing to the limited response time of liquid crystal displays (LCDs), the motion-blurring effect is a critical problem to overcome for LCD applications. Among the available motionblurring reduction methods, frame-rate upconversion (FRUC) presents an outstanding performance; however, it also yields a high computational load, which causes a design challenge for a hardware-efficient FRUC engine running advanced specifications. In this paper, a hardware-efficient FRUC algorithm and architecture were proposed, comprising three core techniques: bidirectional 3-D recursive search (BD-3DRS), spatial and temporal motion vector refinement (ST-MVR), and spatial and temporal overlapped-block motion compensation (ST-OBMC). BD-3DRS provides an initial MV with minor computational overhead. Subsequently, ST-MVR refines the initial MV to generate a more accurate final MV. With this final MV, ST-OBMC has finely processed the interpolated block, especially for the textural smoothness across block boundaries. The experiment results indicated that compared with other sophisticated FRUC methods, computation was reduced by 80% with a minor degradation in a peak signal-to-noise ratio of less than 2%. The hardware architecture was realized using the CMOS technology, and the chip size was 1.20 × 1.20 mm
²
. The working frequency was 270 MHz with a power consumption of 128.08 mW. The maximum throughput was as high as 508 Mpixels/s, which can support a resolution of 3840×2160 from 60 to 120 Hz. Compared with other FRUC architectures, this paper has demonstrated superior hardware efficiencies in terms of area usage and energy consumption.