I. Introduction
The synchronous paradigm is one of the reasons why semi-conductors business flourished in the last decades. It allows a designer to work at a considerably abstract level, usually referred to register transfer level (RTL), ignoring wire and gate delays provided that all events respect a basic set of constraints with respect to a global clock (CLK) signal. However, synchronous circuits are susceptible to problems created by delay uncertainties that are a consequence of process and operating conditions variations. The classic approach to cope with that is to add more margin to the constraints related to the global CLK signal. Unfortunately, contemporary fabrication processes are facing very aggressive variations, and the margins required to account for them are proving to be very pessimist. This problem is further aggravated in large chips, where wider regions of silicon must operate at the same CLK frequency. A negative outcome of this level of pessimism is that designers and architects must assume heavy penalties in area, power, and performance to maintain the traditional usage of the synchronous paradigm.