Domain Wall Interconnections for NML

Nanomagnet logic (NML) is one of the most novel solutions studied as complementary technology to CMOS transistors. Information propagation involves only a change in spin orientation, no charge movement is present. Since the basic element is a nanomagnet, NML circuits have no stand-by power consumption and the ability to mix logic and memory in the same device. While CMOS is a multilayer technology, until now NML is confined to one single physical layer. The consequence is that circuit area grows exponentially due to interconnections overhead. In this paper, we present an innovative solution that drastically reduces the area wasted for interconnection wires relying on the properties of domain walls (DWs). We mix DWs and NML technologies in a unique DW logic (DWL) solution that exploits the advantages of both technologies. The proposed solution is technologically compatible with up-to-date fabrication processes. All the results here presented for the NML logic blocks and the DWs interconnections and their combination are obtained through rigorous micromagnetic simulations. Moreover, we implemented as a case study an high performance adder (Pentium 4 adder) and evaluated its features with increasing parallelism and compared with the simple NML implementation in order to explore the potential of DWL technology at circuit and architectural level. The reduction in circuit area corresponds to a notable reduction in both the latency and power consumption. The improvements in NML technology are shown by both the remarkable performance improvement and new possibilities offered by this novel solution.