Decentralized Thermal-Aware Task Scheduling for Large-Scale Many-Core Systems

Technology scaling has enabled fast increase in the number of cores integrated in many-core systems. However, feature size shrinking also makes large-scale many-core systems vulnerable to thermal failures. Thermal-aware task scheduling is an efficient technique to reduce the run-time temperatures of many-core processors. Most existing thermal-aware task scheduling algorithms leverage centralized scheduling schemes to gather the overall information and generate the task schedule at a center scheduler. Although that scheme can achieve the optimal temperature reduction, however, it faces severe computation bottleneck and communication congestion when the many-core processors evolve to large-scale with hundreds or thousands of cores. In this paper, we propose a decentralized thermal-aware scheduling algorithm to address this problem in large-scale systems. Experiment results on various benchmarks show that our decentralized algorithm achieves significant improvement on scalability (up to 84.3% reduction in monitoring traffic) and similar benefits on temperature reduction (by 5%) when compared with the state-of-the-art thermal-aware scheduling algorithm.

I. Introduction

Technology scaling has enabled a trend in which the number of cores integrated inside one chip grows rapidly [1]. According to the technology road map, thousand-core processors may come into reality in the near future [2]. However, as a negative side effect, technology scaling makes the many-core systems vulnerable to thermal malfunctions due to the increase in power density. Previous studies have shown that the average power density of 65-nm IC is W/mm² [3], which could result in a chip temperature of above 90 °C. As the temperature of the chips rises, thermal-related malfunction phenomenon become more active and can damage the reliability and shorten the lifespan of the chips [4]. Examples of thermal malfunctions include negative-biased temperature instability, gate oxide break down, and electromigration. All those malfunctions pose significant challenges to processor reliability. The shrinking of feature size also brings the problem of dark silicon [5], which severely limits the number of activated components in a chip. As pointed out in [6] and [7], to solve dark silicon problem, traditional solution of using the thermal design power as the power constraint is not sufficient. A more promising solution to the dark silicon problem is to apply thermal constraints to each of the cores in the processors. In conclusion, efficient thermal management techniques are critically demanded by modern processors.