I. Introduction
As the predominant embedded memory technology in modern ICs, static RAM (SRAM) has become the primary consumer of both power and silicon area in nanoscaled IC systems. To integrate the largest possible amount of SRAM, the traditional six-transistor (6T) SRAM bitcell has closely followed the aggressive scaling of CMOS technologies, and has employed nonstandard layouts (pushed rules) to achieve even higher densities. These trends, which according to the latest International Technology Roadmap for Semiconductors update [1], are expected to continue for at least another decade, and are accompanied by an unavoidable increase in process variations that lead to a loss of data stability [2]. Supply voltage () scaling, targeted at lowering the power consumption of both core logic and SRAM blocks, further impedes the robustness of SRAM bitcells due to reduced noise margins and increased sensitivity to device parameter fluctuations. Furthermore, the high density and chip area consumption of SRAM blocks makes them susceptible to soft errors caused by external radiation as well as other single-event-upsets (SEUs), such as those caused by coupled signals, further impairing data integrity [3]. Data stability has always been a central issue in SRAM design, but due to the aforementioned trends, traditional static noise margin (SNM) metrics for ensuring this stability have become impossible to maintain along with the aggressive scaling and density aspirations, and are insufficient for measuring durability in high radiation environments or due to SEUs [2]–[6].