I. Introduction
Duty-cycle correctors (DCCs) are widely used in high-speed devices, such as double data rate (DDR) memories, double sampling analog-to-digital converters, and system-on-a-chip (SoC) applications. Because both the positive and negative edges of the clock are utilized for sampling the input data, these systems require an exact 50% duty cycle of the input clock to ensure that the system meets the timing constraints. However, as the clock signal is distributed over the entire chip with clock buffers, the duty cycle of the clock is often far from 50% because of the unbalanced rise and fall times of the clock buffers, as a result of variations in process, voltage, and temperature. To resolve this problem, many approaches to correct the duty-cycle error and meet system requirements are proposed; for example, an analog pulse-width control loop (PWCL) [1]–[4], [24], an all-digital PWCL [5]–[7], and an all-digital duty-cycle corrector (ADDCC) [8]–[12]. In addition, in some applications, the DCC is combined with delay-locked loop (DLL) located on the output side [13]–[18] to eliminate the phase error caused by the DCC circuit.