A Top–Down Design Methodology Encompassing Components Variations Due to Wide-Range Operation in Frequency Synthesizer PLLs

This paper presents a complete methodology to model, design, and implement wide tuning-range phase-locked loops (PLLs) using a top-down approach. Mathematical equations that illustrate the contribution of the different sources of noise in the PLL are presented. Behavioral models that encompass the nonidealities of the PLL components are described using Verilog-A language. The PLL components are designed, and the noise performance of each component is evaluated using transistor-level simulations. The extracted jitter from the individual blocks is used to find the overall system noise. The proposed methodology considers the variations in the loop dynamics due to changes in the voltage-controlled oscillator gain and noise, frequency divider ratio, and charge pump current. While optimizing the PLL for maximum tuning range, the methodology also considers the tradeoff between the noise, speed, and reference spurs attenuation. The design and implementation of an integer-N frequency synthesizer PLL that covers a continuous frequency range from 156.25 MHz to 10 GHz using a 65-nm CMOS technology is demonstrated in this paper. Measurement results to verify the accuracy of the models and to validate the predictions made by the simulations are provided.