Exploration of Low-Power High-SFDR Current-Steering D/A Converter Design Using Steep-Slope Heterojunction Tunnel FETs

Steep-slope heterojunction tunnel field-effect transistor (HTFET) devices promise new opportunities beyond CMOS in low-power high-performance communication applications. In this paper, the circuit design optimization of a low-power 14-bit 1-GS/s current-steering digital-to-analog converter (DAC) using 0.4/0.3 V mixed-supply HTFETs is explored. Based on the device characteristics comparison and circuit analysis, it is shown in this paper that HTFET endorses significant differences in both I -V and C -V due to the steep-slope tunneling mechanism and a nature of vertically fabricated structure. While such differences significantly affect the circuit design corners, this paper gives the device-circuit co-optimization for the HTFET DAC, reaching at higher current source output impedance, less nonlinear switching glitch distortions, and thus superior spectral performance over the Si-CMOS DAC. HTFET device variation is also discussed, and calibration techniques are adopted for the static matching accuracy.