A Mismatch-Insensitive Skew Compensation Architecture for Clock Synchronization in 3-D ICs

Traditional die-to-die (DTD) clock skew compensation topologies prerequisite matched delay lines or equal through-silicon via (TSV) delays. Unlike previous techniques, the proposed mismatch-insensitive skew compensation architecture can maintain a synchronous clock signal between two dies, while completely eliminating any skew arising from code-dependent mismatch in delay lines or unequal TSV delays. The performance of our design is verified in theory and simulation in light of mismatch/finite resolution of delay lines, clock jitter, phase detector dead zone, TSV delay, and buffer mismatch. Postsynthesis timing verification of this cell-based design was done in a 65-nm CMOS process. Under similar worse case mismatch conditions, the residual skew in the proposed architecture was delimited to 32 ps at 1 GHz, compared with 116 ps for a recent DTD topology, while consuming only 2.1 mW.