A 0.4–1.8-GHz Quarter-Rate Subsampling Mixer-First Direct Down-Conversion RF Front-End

Subsampling down-conversion has not been a popular choice for mixer-first RF front-ends for two interdependent reasons. One, the subsampling down-conversion is inherently heterodyne in nature. Two, as a consequence to one, the passive mixer transparency property can not be exploited for providing impedance matching at the RF port by impedance translation. In this work, an eight-path quarter-rate subsampling (QRSS) mixer-first direct down-conversion architecture is proposed to address these issues. The proposed architecture simultaneously achieves quadrature direct down-conversion and impedance matching by using the third harmonic of the QRSS frequency,
$f_{s}$
. The impedance matching is achieved by exploiting the eight-path passive mixer transparency property. Compared to RF sampling receivers, this architecture employs a sampling frequency
$f_{s}$
three times lesser than
$f_{\text {RF}}$
, saving on the power consumption of nonoverlapping clock generation, distribution circuits, and frequency synthesizer. A test chip is fabricated in 1.2-V, 65-nm CMOS with an active area of 0.32 mm2. The subsampling eight-path mixer, baseband low-noise amplifier (LNA), and
${\text{g}_{m}}$
-cell consume a power of
$800 \mu \text{W}$
, 23 mW, and 3 mW, respectively, for a target bandwidth of 90 MHz. Nonoverlapping clock generation circuit consumes 2–9.2 mW, over the band 0.4–1.8 GHz. The receiver has a double sideband (DSB) noise figure of 4.7 dB, a conversion gain of 22 dB, an in-band (IB)-IIP3 of −1 dBm, and OB-IIP3 of +8 dBm.