Multiphase Digital Low-Dropout Regulators

In this work, multiphase digital low-dropout (MP-DLDO) regulators are designed with resonant rotary clocks (ReRoCs) in order to improve on the tradeoff of conventional DLDOs between current efficiency and transient response speed. The proposed DLDOs are multiphased, coined MP-DLDOs, designed with a clock-gated control technique to provide high current efficiencies along with transient response improvements at GHz frequency levels. The multiple phases within the MP-DLDO are served with ReRoCs that provide: 1) a robust high-speed low-power resonant clock distribution solution for the synchronous elements in the multiphase DLDO architecture and 2) improve the transient response characteristics [dynamic voltage scaling (DVS) speed and voltage ripple] while saving power in the controller circuitry. The proposed MP-DLDOs are distributed across the chip to achieve low voltage ripple. SPICE simulations are performed on post-layout, parasitic-extracted models to evaluate the MP-DLDO architecture on open-source digital cores, with performance metrics that include the voltage ripple reduction, transient response speed improvement, and power savings in the control logic. The proposed MP-DLDO architecture, evaluated on an RISC-V design, demonstrates a DVS speed of 6.5 V/ $\mu \text{s}$ and an output voltage ripple of 21.1 mV (38% reduction when compared to a conventional DLDO) with a sampling frequency of 2 GHz.