A Reusable and Efficient Architecture for QC-LDPC Encoder With Less Expansion Factors

Based on the Richardson and Urbanke (RU) algorithm, the widely used quasi-cyclic low-density parity-check (QC-LDPC) code encodes the parity check matrix (PCM) in blocks, making hardware implementation possible. However, in a QC-LDPC encoding system with multiple expansion factors, storing information bits in excessive register bit widths would reduce the flexibility and throughput of the encoder when the RU algorithm is used. Therefore, this article proposes a novel architecture to reduce the complexity of the encoder by decreasing the number of expansion factors. This architecture optimizes the storage structure of the PCM and the pipeline structure of the encoding core, which obviously improves the flexibility and throughput of the encoder. In addition, this article presents two algorithms to optimize the pipeline structure, decreasing the latency for information bits to enter the encoder and ensuring that the pipeline of the encoding core would not stall. Moreover, the proposed architecture can be applied to encoding systems with multiple expansion factors, such as 5G and IEEE 802.11, and it has been verified on field-programmable gate array (FPGA). Compared with the most advanced solution, the proposed encoder achieves a 77% increase in resource utilization. As a case study, this encoder improves the performance of the soft base station by 2.59 times.