An 8-bit 1.5-GS/s Two-Step SAR ADC With Embedded Interstage Gain

This brief presents an 8-bit two-step successive approximation register analog-to-digital converter (SAR ADC), where the interstage gain is embedded in the second-stage comparison to eliminate the dedicated residue amplifier and its timing cost. Combined with the passive residue transfer technique, the prototype ADC realizes high speed while requiring small overhead. Fabricated in 28-nm CMOS, it operates at 1.5 GS/s and achieves an signal-to-noise-and-distortion-ratio (SNDR) of 43.3 dB at Nyquist rate while consuming 2.32 mW, resulting in a Walden figure-of-merit (FOM) of 12.9 fJ/conv-step.