Process development of 3D WLCSP for ultra-thin CMOS image sensor

For a long time, CMOS image sensor (CIS) packaging has been developing towards lighter weight, better performance and high-density integration. In order to meet the miniaturization of electronic devices, the packaging size of CMOS image sensor products also needs to be reduced accordingly. Therefore, new processes need to be developed to meet the needs of thinner products packaging. In this paper, a kind of three-dimensional wafer level chip scale package (3D WLCSP) for ultra-thin CMOS image sensor using via-last through silicon via (TSV) and temporary bonding technology is reported. The process flow of the 3D WLCSP using via-last TSV, key processes including wafer-level temporary bonding, wafer backside thinning, stress relief etching, Bosch etching, oxide removing, low temperature plasma-enhanced chemical vapor deposition (PECVD) to deposit isolation layer, seed layer deposition, conformal electroplating and passivation, ball grid array (BGA) formation were developed. Key process parameters of the developed 3D WLCSP was characterized by various failure analysis methods. The main failure modes were pad damage and silica isolation layer crack. After process optimization, high packaging yield was obtained. The result indicates that 3D WLCSP with vertical via-last TSV and temporary bonding can provide a low-cost, reliable solution for the ultra-thin CMOS image sensor packaging.