Design and Development of Encapsulation Process for CIS-TSV Wafer Level Package

Wafer-level chip scale packaging (WLCSP) using Via last technology was widely used in CMOS image sensor (CIS) package. Low aspect-ratio tapered through silicon via (TSV) was fabricated for electrical interconnection in mass production, which is not suitable for high IO product. In this paper, a new WLCSP based on vertical TSV structure was introduced. To meet higher reliability requirement, the key encapsulation process was studied by element finite simulation and design of experiment (DOE) for reliability test. The simulation and reliability test results showed the new encapsulation design proposed was a reliable solution for CIS-WLCSP.