Process Optimization based on the Multi-chip RF Integrated Circuits in System Level Packaging

System-level packaging is one of the most popular sealing and testing technologies in the field of integrated circuits. Using MCM(Multichip Module) technology, analog circuits, digital circuits, memory, power devices, photoelectric devices, microwave devices and various chip components can be effectively assembled in the package body, forming a single semiconductor integrated circuit impossible to complete the multi-functional parts, subsystems or systems. The crosstalk noise between lines can be reduced, and the impedance can be controlled easily and effectively, witch improving the overall performance of integrated circuits. In this paper, process optimization is carried out on the basis of multi-chip system-level integration of conventional process flow. At the same time, the failure mode existing in the process of engineering trial production is simulated to locate the failure cause, so as to ensure product quality and realize industrialization.