MRAM Acceleration Core for Vector Matrix Multiplication and XNOR-Binarized Neural Network Inference

Customized hardware for artificial intelligence (AI) applications has gained significance recently. In this study, acceleration core enabled by STT-MRAM is proposed and experimentally demonstrated, which could support complete bit-wise Boolean logic in the read mode. Specifically, two-variables AND for vector matrix multiplication and XNOR for the binarized neural network inference are successfully demonstrated. Both analog and digital approaches are discussed, and a current-input architecture is also suggested to reduce the power consumption for massively parallel computation.