Power efficient hardware accelerators for machine learning, combinatorial optimization, and pattern matching applications

It appears increasingly likely that future performance gains in computing will only be possible by developing novel architectures and circuits, especially those that can efficiently utilize emerging devices in addition to CMOS. I will describe my team’s efforts to co-design across algorithms and architectures to find gains in speed and power. We have utilized the analog and non-volatile nature of memristors to build a Classical Annealer for solving optimization problems more rapidly and at lower energy than current digital systems or Quantum Annealers under development. The presence of intrinsic analog noise in the circuits can be effectively harnessed and dampened as needed in the computing. In another work, we have developed new circuits and assembled architectures that accelerate Finite Automata, enabling rapid pattern matching used in applications from network security to genomics. We forecast significant improvement over CPUs, GPUs, and custom ASICs using the above systems. I will describe the work spanning devices, chip demonstrations, and performance benchmarking.