Analysis of Steep SS Mechanism on PN-Body Tied SOI-FET with 65 nm Thin Box FD-SOI

We investigated the mechanism of the PN-body tied (PNBT) silicon on insulator (SOI) field effect transistor (FET) with a 65 nm thin buried oxide (Box) FD-SOI technology. We clarified the mechanism by which the 65 nm PNBT-SOI-FET shows steep subthreshold slope (SS) only with negative or positive substrate bias (V
_sub
). We compared this behavior with a 200nm SOI-FET technology, which needs no V
_sub
to exhibit steep SS. It coincides with our first measured confirmation of the steep SS on the 65 nm SOI technology. The hole accumulation in channel by the V
_sub
and also the gate voltage is a key for the 65 nm PNBT SOI-FET because the 65 nm SOI-FET is a more fully depleted SOI. The specific shift of the steep SS voltage was also analyzed.