Power Delay Analysis of CMOS Reversible Gates for Low Power Application

At present, circuits with low power and less computation time are in high demand in VLSI technology. In this context, the applications of reversible logic are far-reaching. In this paper, the detailed evaluation of certain reversible gates, namely, Feynman gate, Peres Gate, Modified Fredkin Gate, Modified Toffoli Gate, and TS Gate is set forth. Evaluation comprises of transistor implementation, simulation results and average power and delay measurement. The utilization of TSG to form a completely reversible full adder has also been evaluated in details. The implementations are completely reversible in nature and finds their applications in circuits with low power and high speed which are suitable to implement in silicon.