Adaptive Operation-Based ALU and FPU Clocking

The operating clock period in modern circuits is designated under worst-case operating conditions, in order to ensure error free functionality. To accomplish this goal, designers take into account the timing of the circuit critical path that provides an upper limit for the clock rate. However, that limit imposes heavy performance penalties on the design, since the critical path is not frequently excited during runtime. In contrast with the prevailing methodology, the better-than-worst-case (BTWC) paradigm treats the circuit timing requirements in a more flexible way, as it does not commit to serve the demands of the worst-case scenario. In this work we develop a novel timing analysis methodology inspired by the BTWC approach. Instead of performing the standard critical path analysis, we focus on analyzing the timing requirements of each operation separately. In the sequel we specify an adaptive clock period that is derived by the timing requirements of each supported circuit operation. As a result, we are guaranteed error-free circuit functionality, as no timing violations of individual operations are ever allowed to occur. To this end no error correction mechanisms are required. We verify the proposed methodology by applying it on four different post-layout implementations of ALUs and FPUs. The results we obtain display an average 2.05x throughput increase compared to the implementations operating under the worst-case clock period. We also demonstrate that the area requirements of our methodology are trivial as the overhead is less than 2% of the original design.