Area Optimization of CMOS Full Adder Design Using 3T XOR

GDI (Gate Diffusion Input) is a new technique of low power digital circuit design is proposed. This technique allows minimization of area and power consumption of digital circuits. In this design XOR gate is designed using 3 transistors and CMOS full adder is designed based on two 3T XOR and one 2T Mux. Using 8 transistors the full adder is designed in this paper and voltage scaling also done by reducing supply voltage. In this proposed full adder, the power consumption 4.604μW is achieved and the total area is 144μm².

I. Introduction

With Increasing demand for reliable battery life of digital devices is also demanding for low power consumption digital devices. It has become the major focussed work for designers to design such digital devices in order to meet the requirements of the latest advancements of the technology as these devices mostly include phones, laptops, sensor nodes [1].