FPGA-based implementation of the SHA-256 hash algorithm

SHA-2 is one of the most popular hash functions since it ensures the integrity and the authenticity of information. However, this efficiency is verified at the cost of increasing the computational complexity and the power consumption. To overcome these drawbacks, the hardware acceleration is adopted as a solution in this work to guarantee the best trade-off between rapidity and power consumption. Indeed, this paper focuses on the SW/HW implementation of the SHA-256 hash function using the high level synthesis (HLS) under Xilinx Zynq 7000 based-FPGA. The synthesis results of the SW/HW proposed solution report a gain up to 17% and 73% in execution and power consumption respectively compared to SW case. Moreover, the hardware HLS architecture can reach a gain of 66% in throughput relative to previous work.