A Low-Power Low-Cost On-Chip Digital Background Calibration for Pipelined ADCs

This paper proposes a low-power low-cost on-chip digital background calibration for a pipelined ADC. This new redundant-stage calibration algorithm reduces the effect of quantization noise and can be applied for multiple stages; hence, it improves the calibration accuracy and is easily implemented fully on-chip with low power and low hardware cost. We realize the proposed calibration technique in a prototype 12-bit 250-MS/s pipelined ADC fabricated in a 55-nm technology. The measured results show that the prototype ADC, with an active area of 1310 μm × 510 μm, achieves an signal-to-noise-and-distortion ratio of 66.7 dB [effective number of bits (ENOB) = 10.8 bit] and consumes a total power of 85 mW with a sampling rate of 250 MS/s after applying our digital calibration, where the on-chip digital calibration circuit consumes only 5 mW and an active area of 360 μm × 510 μm.