Hardware Efficient Function Computation Based on Optimized Piecewise Polynomial Approximation

This paper presents an optimization method for function computation based on piecewise polynomial approximation with truncated multipliers. The proposed design jointly considers all the error sources, including the approximation errors, quantization errors, truncation errors, and rounding errors. Thus, the total error budget can be utilized more efficiently and the bit widths of the hardware components can be optimized, leading to significant area improvement. Due to the trade-off between the size of lookup tables (LUT) and the area of arithmetic components, we consider two minimization goals: LUT size and total area. Experimental results show that the proposed optimization method has chance of finding better hardware design variables compared with state-of-the-art designs.