A 10-Bit Split-Capacitor SAR ADC with DAC Imbalance Estimation and Calibration

This paper presents a 10-bit SAR ADC with a sampling rate of 200 MS/s. To reduce area and power consumption, the ADC adopts a split-capacitor DAC, where the gain error is estimated and subsequently removed by means of a PRBS signal injected into the DAC and detected at the ADC output. The ADC has been designed and fabricated in a 22nm FD-SOI CMOS process, and achieves an SNDR of 48.7 dB and an SFDR of 66.7 dB for input frequencies up to the sampling frequency, with a power consumption of 4.3mW and an FoM of 152 dB.