A 3GS/s Highly Linear Energy Efficient Constant-Slope Based Voltage-to-Time Converter

This paper presents a high speed highly linear energy-efficient constant-slope based voltage-to-time converter (VTC). By combining sample-and-hold with constant charging process, we achieve precise sampled step and linear charging ramp concurrently without using the extra control clock. Simple calibration has been implemented to overcome conversion gain variation due to process-voltage-temperature (PVT) variation. The post-layout simulation results show that the SFDR/-THD of the proposed VTC reaches 58.7dB/56.3dB at 3GS/s near Nyquist (typical corner). The VTC achieves 144ps output range with 0.83mW power consumption at 3GHz. It occupies an active area of 41.3um × 34.4um implemented in 65nm CMOS.