A Ling-Enhanced Adder for IEEE-compliant Floating-Point Multiplication

This paper proposes the design of a twos complement adder optimized for floating point multiplication based around extensions to parallel prefix tree adders. After the final addition of a floating point multiply, the MSB is used to determine if the product overflows. The delay of this bit must be shorter than all other bits of the product in order to optimize the performance of the overall multiplier. This design builds two prefix trees in order to minimize delay computing the MSB and reduce the size and power consumption of rest of the adder. Layout results are shown for adders used in IEEE 754 double precision multipliers using Global Foundries 14nm process and the ARM 10.5 track standard cells. The proposed design improves adder delay by 8% with a decrease in area and power consumption.