MSB-First Distributed Arithmetic Circuit for Convolution Neural Network Computation

This paper presents a novel circuit implementation for convolution filters and rectified linear activation function used in deep neural networks. By conducting computation in an MSB-first bit-serial manner, it can predict earlier if the outcomes of filter computations will be negative and subsequently terminate the remaining computations to save power. It also stores pre-computed partial products into look-up tables to eliminate the need for multiplier circuits, leading to hardware efficient implementation. The proposed circuit is implemented on an FPGA and it shows significant power and performance improvements compared to a conventional design implemented on the same FPGA.