Compute-in-Time for Deep Neural Network Accelerators: Challenges and Prospects

Time-domain (TD) accelerators leverage both digital and analog features, thereby enabling energy-efficient computing and scaling with CMOS technology. This paper reviews state-of-the-art TD accelerators and discusses system considerations and hardware implementations, including the spatially unrolled and recursive TD architectures. Additionally, the paper analyzes the energy and area efficiency of the TD architectures for varying input resolutions and network sizes. This analysis provides insight for designers into how to choose the appropriate TD approach for a particular application.