Low Power Quaternary Adder Using CNFET

Binary logic and MOS devices have been in use since the inception of the design era, but now due to advancement in VLSI industry binary logic has become tedious and complicated. To overcome this challenge Multi-valued logic (MVL) such as ternary and Quaternary Logic (QTL) can be used. MVL designs have an advantage over binary logic designs with respect to the chip area and the complexity of interconnection. In this paper, we present the design and performance analysis of QTL Full Adder (QFA) using Carbon Nano-tube Field Effect Transistor (CNFET). For design purposes, we have used the Stanford Virtual-Source Carbon Nanotube Field Effect Transistor Model version 1.01 with sub 10nm CNFET technology. The design tool used for simulation is Cadence Virtuoso. The proposed QFA design has been compared against the existing CNFET based QTL designs and it is found that the proposed QFA design is 97-98% better in terms of Power Delay Product (PDP) and Energy Delay Product.