Simulation of Triple Gate Spin Field-Effect Transistor and its Applications to Digital Logic

The simulation of Triple Gate Spin-FET having Indium Arsenide as its channel material is performed using its mathematical model in this paper. The simulation results are validated using dc simulations. Later by setting the suitable channels and various other parameters like spin injection, spin detection etc., diverse logic functions are attained. the different inputs are given at the various gate terminals. The functions obtained are implemented using only one multi gate spin-FET. If the same functions would be implemented using conventional CMOS, the number of devices required will be much higher. The functions obtained are also proficient in terms of power and speed as paralleled to the design using VLSI CMOS. The performance of the proposed designed is compared to the already existent VLSI CMOS for the same logic functions in a table.