Timing Domain Crossing using Muller Pipelines

The increasing complexity and modularity of contemporary systems, paired with increasing parameter variabilities, makes the availability of flexible and robust, yet efficient, module-level interconnect instrumental. In this context Globally Asynchronous Locally Synchronous (GALS) systems offer a viable alternative to classical strictly synchronous interconnect. However, with this concept a need for reliable interfaces between different clock and timing domains arises. In this paper we propose a novel approach for timing domain crossing interfaces which are able to safely transfer (read) tokens (i.e., zero-bit messages) from a synchronous into an asynchronous timing domain and vice versa. At its core the new approach uses a Muller pipeline where read tokens are synchronously written to and read from. Doing this in a way that does not lose any tokens, requires the synchronous timing domain to have exact state information about the fill-level of the Muller pipeline (i.e., is it safe to perform a write or read operation). We thoroughly analyze how this state information can be obtained and propose a simple pipeline sampling model. Furthermore we discuss what timing constraints these concepts rely on and how to deal with metastability that inevitably appears at such interfaces. One possible use of the proposed structures is the control path of synchronous/asynchronous or bisynchronous FIFOs, which we use to illustrate the principle and show the practical feasibility.