Parallel FPGA-Based Architecture for Real-Time AUV Robust Control

This paper introduced a real-time control scheme using parallel FPGA technique and H
_∞
algorithm. H
_∞
controller is very popular in AUV control applications due to its robust performance in the presence of uncertainties. However, discrete H
_∞
controller can be viewed as, essentially, a series of floating-point matrix multiplication which requires efficient computing power to maintain real-time control performance. Generally, Due to the limitation of serial computing mechanisms, the conventional embedded control system can not consider both computing speed and flexibility. FPGA has a strong parallel processing ability and real-time operation speed. Therefore, a structure of parallel matrix multiplication based on the FPGA platform was proposed in this paper to improve the computing ability of the AUV embedded system and to solve the real-time problem. To prove the prototype architecture, closed-loop simulations were carried out based on SoC-FPGA. A 5-dimensional robust controller was implemented for the CISCREA AUV yaw control scenario, and experimental results show that controller iterative frequency can reach up to 0.495MHz when FPGA operates at 50MHz clock.