A 60-GHz Digital Sub-Sampling Integer-N Phase-Locked Loop

Digital phase-locked loops (DPLL) are finding new applications in highly demanding contexts such as frequency synthesis for millimeter-wave (mm-wave) communications and clock generation for ultra-high-speed wireline transceivers. In a typical DPLL, however, a time-to-digital converter (TDC) with fine time resolution, high linearity and high dynamic range is required to meet stringent noise and spur performance requirements, which negatively impacts the power consumption in a DPLL. A bang-bang phase-detector (BPD) outperforms a multibit TDC in terms of its' jitter-power tradeoff, but its' highly nonlinear phase detection characteristic limits the locking speed of the loop. This research explores the design of a 60 GHz digital subsampling phase-locked loop that uses a BBPD loop for frequency tracking and a coarse TDC loop for fast frequency acquisition. A prototype of the DPLL is designed in a 28-nm CMOS technology and extensive simulation results are provided.