A Low-Power 5 GS/s 6b Flash ADC with 2-Stage Multi-Bit Search and 2× Time-Domain Interpolation

This paper presents a low-power 5 GS/s 6-bit flash analog-to-digital converter (ADC) fabricated in a 28-nm FDSOI CMOS technology for RF wideband radio receiver and high-speed serial link applications. The flash ADC leverages a 2-stage multi-bit search and a 2x time-domain interpolation to improve the ADC power efficiency and alleviates the input bandwidth degradation. A 0.5-bit redundancy is utilized in the first comparator stage to relax the settling requirement of the track-and-hold (T/H) buffer when utilizing the proposed ADC in a time-interleaved configuration for higher sampling rate applications. Measurement results show that the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 30.9 dB at Nyquist frequency with a power consumption of 14.43 mW, translating to a Walden figure-of-merit (FOM) of 99 fJ/conv.-step.