Vertical Power SiC MOSFETs with High-k Gate Dielectrics and Superior Threshold Voltage Stability

Despite the recent progress in SiC power MOSFET technology and its commercialization, the defective MOS interface still hampers the exploitation of the full potential of these devices. We present results using our high-k gate stack technology that shows significantly reduced density of interface states (D
it
) along with superior threshold voltage (V
TH
) stability for low voltage SiC power MOSFETs. The findings indicate virtually no V
TH
-shift during static characterization as function of the starting gate voltage and its ramp. Furthermore, dynamic switching results show virtually no threshold voltage shift for $V_{GS,start} \gt -12$V.