Design Consideration of Low Capacitance SiC JMOS for Adapting High-Speed Operation

In order to prevent bipolar degradation and improve the performance of body diode in SiC MOSFET, JBS embedded SiC MOSFET technology is attracting researchers’ attention. In this paper, the discussion focuses on JMOS, where the major feature is retaining the same chip size and fabricating process flow while introducing a JBS rectifier into the unit cell of a conventional DMOS. However, in previous work, it is surprising to identify that the characteristics of parasitic capacitances, C
oss
and C
rss
, are different between JMOS and DMOS. According to the previous research, we have already discovered the reason why C
oss
of JMOS is lower than that of DMOS. Yet, the difference in C
rss
still has not been recognized clearly. Therefore, a hypothesis has been raised to explain how various designs to influence C
rss
in this work. Then, we simulate various structures of diverse designs on the Silvaco TCAD platform and discuss these results. Furthermore, the result from TCAD has exported and transferred into LTspice model for evaluating the effect of different designs in double-pulse test circuitry. Finally, this work has also implemented the diverse designs in practical foundry and verifies the effect on the electrical characteristics of each design.