Multi-trench-gate Cell Concept for Low Voltage Superjunction Power MOSFETs

Multi-trench-gate (multi-TG) cell concept is proposed for below 60V class superjunction (SJ) power MOSFETs. The proposed SJ cell improves manufacturability by relaxing too aggressive column pitch narrowing while keeping specific on-state resistance R
sp
reduction. Two-TG SJ cell is designed by fully utilizing TCAD and over 20% Rsp reduction with good charge imbalance margin against our 4th generation single gate SJ cell is obtained. The 1st experimental demonstration results in 13% R
sp
reduction and slightly lower BV
dss
than target because of the insufficient tuning of column implantation mask patterning and insufficient optimization of design parameters of termination region.