High-Level Synthesize of Backpropagation Artificial Neural Network Algorithm on the FPGA

The studies related to the synthesis of backpropagation artificial neural network algorithms are still based on the direct synthesis, so it requires an effort to modify the algorithm into hardware language so it can be optimized, synthesized and implemented into the FPGA. The High-Level Synthesis (HLS) is a software compiler which able to convert C specifications into Register Transfer Level (RTL) form, which can be synthesized into FPGAs. So the designer can focus on the optimization of the algorithm itself, including speed and resource optimization. This paper discus the results of the synthesis of backpropagation artificial neural network algorithms using HLS (High-Level Synthesis) software. The C-synthesis results based on the Zynq7000 FPGA showed an accuracy of 96.56%, were able to be clocked with a period of around 9.37 ns, with resource usage of 18% for BRAM_18K, 67% for DSP48E, 25% for FF and 71% for LUT. While the utilization difference is not significant compare to the previous studies, the optimization effort using an HLS tools need to be taken into account.