A Novel VLSI Architecture of CORDIC Based Image Registration

Now-a-days real-time image registration (IR) has been emerged as a potential field of research by virtue of its vast applicability. Despite such high demand, till now, most of the real-time IR based applications rely upon software based tools for performing the image registration task. Those software based tools need to be highly sophisticated to comply with the performance of any real-time system. Naturally, the real-time IR system is costly and power consuming in nature. The only cost-effective solution for this is to develop a dedicated hardware catering real-time IR. In this article, a novel VLSI architecture for real-time IR has been presented. With an ardent focus on making the proposed architecture cost-economic, the transform model estimation (TME) step of IR method is realized using co-ordinate rotation digital computer (CORDIC) technique which is popularly regarded as hardware efficient. The proposed CORDIC based TME architecture is utilized to realize the state of the art VLSI architecture of real-time IR in terms of dedicated hardware which has been implemented onto Zynq UltraScale+ MPSoC series FPGA. The performance of the proposed and FPGA-implemented VLSI architecture of the IR has been compared with its software based counterpart using MATLAB. The proposed VLSI architecture of IR has been proved to outperform the software based realizations in terms of area, power consumption and speed of operation, thereby emerging as a cost-economic solution for the real-time IR.