Scalable Chiplet package using Fan-Out Embedded Bridge

As silicon scaling closer to physical limit, future reduction of the gate oxide does not lower down the cost per transistor. But the demand of higher functionality and lower cost of electronic devices do not slow down. Development of electronic devices metaphor to high-density package integration. What the electronic industries do is to break down a large die to a chiplet-based devices for improving yield and lower the total cost. Chiplet package become a key technology to continue Moore's law. With the intensive researches, multiple chiplet packages are evolved such as multi chips on Si interposer using TSV (2.5D), die to die stack on each other (3D), Fan-Out Multi Chip Module (FOMCM), and EMIB (Embedded Multi-Die Interconnect Bridge). These packages are developed for the server, high performance computing, router, and switcher markets. But, the integration of high bandwidth memory devices and multiple ASIC dies together requires very high I/O counts and signal transmitting. Thus, a much higher RDL (Redistribution Layer) layer counts, finer bump pitch and smaller line- space (L/S) are designed. Each of these chiplets has its limitations. Large 2.5D package has its cost concerns on large Si interposer and mismatch of the Si interposer with substrate on reliability test. Whereas, large FO-MCM technology is limited by finer L/S and higher layers count of RDL. Presently, the package is heading the bottleneck at 1/1 μm L/S, 5 layers RDL and 2 reticle size chip module. As for EMIB technology, it is constrained by L/S that could only down to 5/5 μm. In this paper, we have successfully developed a scalable chiplet package technology, namely Fan-Out Embedded Bridge (FOEB). This chiplet package enables near monolithic short reach BEOL connections between dies. FOEB can have multiple RDL layers and Si bridge that has much finer L/S for interconnection. In addition to, multiple dies can be bridged together into one single chip module. In this paper, the demonstration of FOEB test vehicle, which integrate chips by 1 ASIC die and 4 memory dies (1+4) with 4 embedded bridge dies on mold-based interposer, 3 layers of RDL are presented. By comparing packages using FOMCM and 2.5D to fabricate. FOEB package has much lower warpage and 2× lower stress value as compare to 2.5D. But similar to FOMCM. Owing to this reason, the FOEB chiplet package were tested 2x longer temperature cycle with condition-G without single failure as compared to 2.5D. The assembly yield of FOEB is comparable to FOMCM. And much higher than that of EMIB. Assembly of FOEB chiplet package adopts organic interposer. The wafer warpage changes from concave to convex shape after die attachment on the molded interposer. This limits some of the machines handling and induces wafer cracking. By properly select the right molding compound, and glass carrier CTE, we have successfully developed this FOEB chiplet and validated through reliability test. This chiplet allows us to scale the package to much higher I/O density, finer L/S, higher RDL layers, and number of dies that can be integrated into one single chip module.