Fan-In Panel-Level with Multiple Diced Wafers Packaging

In this study, a very high-throughput and low-cost packaging method for fabricating the fan-in chip scale package is presented. Emphasis is placed on the utilization of the existing PCB (printed circuit board) panel carriers and the corresponding PCB equipment for making the RDLs (redistribution-layers), vias, UBM (under bump metallurgy), contact pads, and solder mask of the package. Since all the PCB panels are in rectangular shape, some of the device wafers are diced into two or more pieces so the panel is fully utilized.