OpenCAPI Memory Interface Simulation and Test for Differential DIMM Channel with SNIA SFF-TA-1002 Connector

DDR5 Differential DIMM (DDIMM) is being defined in JEDEC and uses OMI as a host interface with the data transfer rate per data differential pair being specified at 25.6Gb/s minimum at present and at 51.2Gb/s maximum in the future. This is a significant data rate increase for DRAM modules over conventional single-ended data transferring DIMMs. For example, the DDR5 LRDIMM data transfer rate per pin is 3.2Gbps. This study utilizes the DDIMM early engineering samples with DDR4 to evaluate the OMI channel running at 25.6Gb/s.Validating the DDIMM PCB wiring for the high-speed differential memory bus requires accurate high-speed link simulations. These simulations require accurate models representing differential wiring in the DDIMM PCB stack up. The models must be built using not only representative physical dimensions but also accurate frequency dependent material properties obtained through PCB characterization. The simulation results of the initial study in 2018-19 concluded that the typical Copper Clad Laminate (CCL) and prepreg material used in the industry standard R/LR DIMM leads to signal integrity degradation relative to a better reference material at 25.6Gb/s OMI bus data rate[l]. This paper is based on 2019-20 DDIMM test results and the full channel time domain eye diagram analysis with BER at 10
^˄
-15 assuming an improved DDIMM PCB stack up with hybrid structure to satisfy signal integrity while minimize the material cost premium.DDIMM will be paired with the Storage Networking Industry Association (SNIA) SFF-TA-1002 high speed connector which differs significantly from the JEDEC RDIMM connector for improved electrical signaling characteristics. The connector to PCB interface design has been studied as it is of utmost importance for achieving good signal integrity[l]. The DDIMM test samples for this study include the high speed connector to PCB interface attributes such as Plated Through Hole (PTH) in ground contact pad, ground plane void under OMI signal pad and tie bar removal.The challenges of DDIMM PCB mechanical interaction with SFF-TA-1002 connector have been highlighted in the initial study[l]. This study uses early engineer samples to evaluate the insertion/extraction performance. Future work will use test vehicle of PCB/connector pairs to characterize the high speed electrical performance and evaluate the contact reliability.In summary, this paper presented the full channel simulation result assuming an improved DDIMM PCB material/stack-up at 25.6Gbps for comparison with the performance that baselined in the initial work with the industry standard PCB material. Physical characterization of the engineering samples has been conducted to baseline the DDIMM PCB to connector contact interface. Electrical test is performed with early engineering samples in IBM high speed system to verify the simulation result.