Waferscale S-MCM for High Performance Computing

This paper describes a novel strategy to combine laser direct write (LDW) and optical lithography (I-line) to fabricate 200 mm waferscale superconducting multi-chip modules (S-MCM) for interconnecting multiple active superconducting electronics chips based on single flux quantum (SFQ) logic for next generation cryogenic processing systems. The packaging roadmap includes the development of S-MCM (48 mm x 48 mm) using a nearly full I-line reticles, followed by reticle stitching to fabricate the largest possible stitched S-MCM (96 mm x 96 mm) using a four mask/layer process. The stitching process starts with sequential exposure of multiple I-line photomasks, with small overlap (stitched area), to realize larger combined circuit areas for design- critical S-MCM layers with minimum linewidths of 0.8-1 gm. The packaging roadmap further extends the S-MCM size utilizing laser direct write (LDW) lithography to make wider (> 1 gm) features such as fan-out circuits, extending the stitched circuit area to include the entire 200 mm wafer as a single S-MCM. Process control monitors (PCM) include snake/comb test structures, critical dimension (CD) cells, transmission lines, daisy chains etc. Niobium-indium-based microbump technology was developed to demonstrate full-size (20 x 20 mm
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) SFQ flip-chips on an S-MCM with low 4 K interconnect resistance (50-100 μΩ) at the SFQ chip to S-MCM interface. Confocal micrographs show a uniform niobium-indium microbump-based interconnect network and X-ray images show the desired deformation of niobiumindium microbumps after flip-chip bonding. Full-size (20x20mm
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) flip-chip daisy chains with 10k and 100k bumps maintained high Nb critical current post-bonding (> 50 mA), demonstrating a viable platform for building larger superconducting computing systems.